The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...

SANTA CLARA, Calif.--(BUSINESS WIRE)--SiFive, Inc., the gold standard for RISC-V computing, today announced that the company has partnered with Kinara to create a USB-based enablement board that ...

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...

A new technical paper titled “Test-driving RISC-V Vector hardware for HPC” was published by researchers at University of Edinburgh. “Whilst the RISC-V Vector extension (RVV) has been ratified, at the ...

The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary ...

RISC-V is used to design anything from smartphone chips to advanced processors for AI Chinese chip design firms have embraced it Beijing has yet to mention it in policy Shares in Chinese chip firms ...

Many have waited years to hear someone like Prahlad Venkatapuram, Senior Director of Engineering at Meta, say what came out this week at the RISC-V Summit: “We’ve identified that RISC-V is the way to ...

Old-timers might recall the idea of "RISC" as a once-upon-a-time processor design ideology. RISC processors were mostly used for servers from Sun Microsystems, DEC, and other companies of a bygone era ...