Verification engineers continually report that up to 70% of the total engineering time spent on verification is consumed by debug, particularly when relying on disparate tools across multiple vendors.

验证是 SoC 设计不可或缺的核心，而 SoC 功能的不断增加也导致其设计变得更加复杂。SoC 的状态空间以及验证空间随着门数的增加而呈指数级增长，因此对总验证吞吐量、查找和修复错误的需求也呈指数级增长。 瑞萨电子的验证团队就面临着这样的挑战。

9月15日消息，楷登电子（美国 Cadence 公司）今日宣布推出 Cadence® Verisium™ Artificial Intelligence (AI)-Driven Verification Platform，整套应用通过大数据和 JedAI Platform 来优化验证负荷、提高覆盖率并加速 bug 溯源。Verisium 平台基于新的 Cadence Joint ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Renesas has deployed the new Cadence ® Verisium ™ Artificial Intelligence (AI)-Driven Verification ...